The present invention relates to a complementary metal oxide semiconductor (CMOS) type output buffer circuit for driving a high current load, and more precisely, it relates to a buffer circuit which suppresses its output noise and an excess current which inherently runs through the CMOS circuit at an instant when input signal is switched from ON to OFF or vice versa.
Recently as the integration of circuitries in an IC (integrated circuit) increases, the logic circuits of the IC designed to be operated by as little power as possible, while the loads driven by the IC are unchanged or increasing because many loads are driven at a same time. Therefore, the buffer circuits provided in the IC are becoming large and are increasing in number to drive such loads. But as the output of the buffer circuit becomes large and its switching speed is increased, a problem is caused by switching noise of the output buffer circuits. Namely, quick change of a large current in the output buffer circuit induces noise, and causes malfunctions of operation in the inner logic circuits of the IC. Such a trend is especially becoming severe in large scale integrated circuits (LSI), in which a chance increases that many of the output buffer circuits are operated at a same instant, thus increasing the noise.
A conceptual circuit diagram of an exemplary output buffer circuit used in many of ICs is shown in FIG. 7, wherein a vertical chained line indicates a border between the LSI and outer circuit. The left hand side of the chained line indicates the inside of the IC, it may be considered as an IC chip or package, and the right hand side indicates the outside of the IC. The output signal of the inner circuit (not shown) of the IC appears at a circuit point 1, which is an input terminal for the output circuit. In this example, the output circuit is composed of two stages of inverter, the first stage inverter 2 is a smaller size inverter which operates as a driver circuit, and the second stage is a large inverter composed of series connected p and n channel FETs (field effect transistors) 31 and 32 respectively. Gates of these FETs are connected in common and receives the output of the first inverter 2. Drains of the FETs 31 and 32 are connected to each other and provides the output. 41, 42 and 43 . . . are loads driven by the output circuit 3. They are connected in parallel in this example.
In ordinary ICs, the FETs 31 and 32 are designed to have a current handling capacity large enough to provide current for driving the loads. Accordingly, the ratio (W/L) of the gate width (W) to the gate length (L) of the FETs is designed to be large in order to reduce their internal resistances to provide large current. But in such prior art circuits, there occurs a problem of noise when the load is driven ON and OFF caused by a quick change of the driving current I running through the output buffer circuit. As mentioned before, such problem is further emphasized in LSIs because there increases a chance that many of such large output currents from many output circuits are switched ON and OFF at the same time.
An attempt to overcome such problem has been proposed by S. Fujii et al. They intend to reduce the noise by decreasing dI/dt a time derivative of the current in the output buffer circuit. This has been done by slightly blunting the wave form of input signal to the output buffer circuit. By such blunting, the overall switching speed of the output circuit is not affected substantially, because most of the switching speed of the output circuit is determined by saturation current of the output buffer circuit, and only the noise has been reduced. More detail is disclosed in, for example, Japanese Laid Open Patent 60-136238 (published on July 17, 1985) by S. Fujii etal, and the same is now issued as U.S. Pat. No. 4,272,266. It is also applied to EPC as European Pat. Appln. No. 84308891.5.
By the method proposed by Fujii et al, the noise of the output buffer circuit has been suppressed cleverly, but there still remained another problem. That is the excess current which instantaneously runs through the output buffer circuit when the inverter circuit is switched from ON to OFF or vice versa. There is an instance during which both of the series connected p and n channel FETs in the output buffer circuit become conductive, so an excess current runs from the positive voltage source through the CMOS circuit to the negative side voltage source, and it increases when the internal resistance of the FETs of output buffer circuit is reduced. Such excess current is undesirable for an IC because it increases the loss of the circuit and causes a temperature rise of the IC chip. It also induces noise, since such excess current becomes a sharp pulse. Such phenomena are known in the art, and several ideas to avoid such excess current have been proposed. For example, U.S. Pat. No. 4,164,842 by Ebihara discloses a method to insert a delay circuit in respective input side of the p and n channel output FETs for slightly shifting the input pulses from each other when they reach to respective gate of the output FETs, to eliminate the instance during which both of the series connected p and n channel FETs become conductive at the same time.
But there was not a simple way to avoid both the noise and the excess current.